In recent years, it has become difficult to secure an operation margin of a circuit characteristic due to an increase in a variation in a semiconductor device characteristic, particularly, a field effect transistor characteristic (hereinafter a “transistor variation”) associated with miniaturization.
If an assumed circuit operation margin is unable to be secured due to a transistor variation, a yield degradation occurs, thus, there are cases in which a circuit area is increased to be larger than assumed if a circuit is designed to secure an operation margin so that a yield degradation does not occur.
Therefore, there is a demand for a countermeasure of specifying a cause of a transistor variation, taking a processing countermeasure to suppress a variation, and introducing a circuit robust to the transistor variation.
There are various factors as the cause of the transistor variation, but particularly, influence of variations in a gate length and an effective gate length caused by patterning exceeding a wavelength limit of lithography is large, and thus it is necessary to quantitatively detect the gate length variation for the countermeasure.
In other words, if it is possible to quantitatively detect the gate length variation accurately, a countermeasure of optimizing a processing process such as lithography, a gate process, and a thermal process that cause the gate length variation and managing a mass-production process so that the variation is minimized or making influence of the variation uniform is possible.
For the mass production management of the gate length, a technique of picking some wafers after the gate lithography or the gate process, measuring gate length dimensions of several to several tens of spots in a wafer surface, and performing management so that the variation falls within a preset specification is common.
However, if it is desired to perform length measurement in all wafers or in various spots, it takes time, and at this stage, it is unable to specify whether or not the gate length variation affects an electrical characteristic variation of a transistor.
In this regard, a technique of placing a test device that extracts a gate length electrically in a scribe, performing a test process of measuring a gate length electrically after performing a processing process, and performing management so that the variation falls within a preset specification range has been proposed (see Non-Patent Document 1).
In this case, one test device is arranged in one shot which is commonly an exposure unit of lithography, and although it is measured in the test devices of all shots, there is a detection limit to covering a variation within a wafer surface.
As a countermeasure against the technique disclosed in Non-Patent Document 1, a technique of placing a test device in a chip rather than a scribe is considered.
However, in a case in which the test device is arranged in the chip, a dedicated measurement pad for monitoring an electric current of the test device is additionally necessary, and in a case in which it is desired to perform measurement using a logic tester, a memory tester, or the like, it is difficult to secure sufficient measurement accuracy, and it takes time to measure.
In this regard, a method of arranging a monitor circuit using a ring oscillator (RO) as a test device to be installed in a chip has been proposed (see Non-Patent Document 2).
Since the ring oscillator is capable of performing digital output, an output pad can be shared with other monitor circuits by switching a test mode through a test control circuit, and it can be configured without adding a pad.
Further, it is also possible to place the monitor circuit in an arbitrary region in the chip, and compatibility with a chip design is high.
Further, it is easy to measure the digital output of the ring oscillator in the logic tester or the like, a measurement time is also shorter than that in the current measurement, and it is possible to monitor the ring oscillator at the same time as a chip sorting test, and thus detection sensitivity for the variation within a wafer surface is high.
In the technique disclosed in Non-Patent Document 2, a frequency variation of the ring oscillator when a configuration of the ring oscillator is changed to an inverter, a NAND, a NOR, or the like or a fan-out is changed is investigated.